1. Field of the Invention
The present invention relates to a semiconductor device and, more specifically, a semiconductor device in which a plurality of elements identical in structure are arranged in an array.
2. Description of the Background Art
FIG. 13 is a block diagram showing the configuration of a conventional static random access memory (SRAM). With reference to FIG. 13, the conventional SRAM is described.
The SRAM shown in FIG. 13 includes a memory cell array 1001, a second dummy memory cell array row 1002, a second dummy memory cell array column 1003, a first dummy memory cell array row 1004, a first dummy memory cell array column 1005, a word driver block 1006, a row decoder block 1007, a switch block 1012, and a sense amplifier block 1015.
The memory cell array 1001, the second dummy memory cell array row 1002, the second dummy memory cell array column 1003, the first dummy memory cell array row 1004, and the first dummy memory cell array column 1005 have the configuration shown in FIG. 14. Specifically, in the memory cell array 1001, 256 bit lines BL[f] (f is an integer from 0 to 255) and 256 inverted bit lines NBL[f] are alternately arranged in the height direction, while 128 word lines WL[w] (w is an integer from 0 to 127) are arranged in the width direction. Memory cells MC are arranged in an array, and each memory cell MC is placed between a bit line BL[f] and an inverted bit line NBL[f] that have the same value of f.
Also, the memory cell array 1001 is surrounded by the second dummy memory cell array row 1002, the second dummy memory cell array column 1003, the first dummy memory cell array row 1004, and the first dummy memory cell array column 1005. The second dummy memory cell array row 1002, the second dummy memory cell column 1003, the first dummy memory cell array row 1004, and the first dummy memory cell array column 1005 each include dummy memory cells D1 and D2 that do not operate. The dummy memory cells D1 and D2 are connected to either one of a set of the dummy bit line DBL[0] and the inverted dummy bit line DNBL[0], a set of the dummy word lines DWL[2] and DWL[3], a set of the dummy word lines DWL[0] and DWL[1], and a set of the dummy bit line DBL[1] and the inverted dummy bit line DNBL[1].
As shown in FIG. 13, the word driver block 1006 is placed to the left of the first dummy memory cell array column 1005 shown in FIG. 14. Further, the row decoder block 1007 is placed to the left of the word driver block 1006. FIG. 15 is an illustration showing the circuitry configuration of the row decoder block 1007 and the word driver block 1006.
As shown in FIG. 15, the row decoder block 1007 has arranged therein a plurality of row decoders. The word driver block 1006 is provided with a plurality of word drivers 40-k (k is an integer from 1 to 128) correspondingly to the row decoders. Each word driver 40-k is a Complementary MOS (CMOS) inverter formed of one N-ch MOS transistor 30-k and one P-ch MOS transistor 31-k. Each word driver 40-k switches a potential of the connected word line WL[w] High or Low.
Here, with reference to FIG. 16, an arrangement of the transistors in the word driver block 1006 is described below. FIG. 16 is an illustration showing an arrangement of the N-ch MOS transistors 30-k and the P-ch MOS transistors 31-k in the word driver block 1006. In FIG. 16, hatched rectangular portions each represent a transistor diffusion layer, while hollowed rectangular portions each represent a gate electrode.
An N-ch MOS transistor 30-k and a P-ch MOS transistor 31-k forming a word driver 40-k are arranged side by side in the width direction as shown in FIG. 16. Also, pairs of one N-ch MOS transistor 30-k and one P-ch MOS transistor. 31-k are arranged in the height direction at a spacing approximately equal to that of the memory cells MC arranged in the memory cell array 1001 in the height direction.
Next, the switch block 1012 and the sense amplifier block 1015 are described. As shown in FIG. 13, the switch block 1012 is placed at the lower side of the first dummy memory cell array row 1004, and the sense amplifier block 1015 is placed at the lower side of the switch block 1012. FIG. 17 is an illustration showing a circuitry configuration of the switch block 1012 and the sense amplifier block 1015.
The 256 bit lines BL[f] and the 256 inverted bit lines NBL[f], which are arranged longitudinally across the memory cell array 1001, extend to as far as the inside of switch block 1012. In the switch block 1012, 512 P-ch MOS transistor 50-n (n is an integer from 1 to 512) and 512 N-ch MOS transistor 51-n are formed. Each bit line BL[f] and inverted bit line NBL[f] is connected to one P-ch MOS transistor 50-n and one N-ch MOS transistor 51-n to form a switch 60-s (s is an integer from 1 to 512).
Also, each switch 60-s is connected to a data line DL[p] (p is an integer from 0 to 127) and an inverted data line NDL[p] extending to the inside of the sense amplifier block 1015. Therefore, 128 data lines DL[p] and 128 inverted data lines NDL[p] are provided in total. Furthermore, in the sense amplifier block 1015, 256 P-ch MOS transistors 52-m (m is an integer from 1 to 256) and 256 N-ch MOS transistor 53-m are formed. Each data line DL[p] and inverted data line NDL[p] is connected to two P-ch MOS transistors 52-m and two N-ch MOS transistors 53-m forming a sense amplifier 70-r (r is an integer from 1 to 128).
FIG. 18 is an illustration showing an arrangement of transistors in the switch block 1012 and the sense amplifier block 1015. In the switch block 1012, pairs of one P-ch MOS transistor 50-n and one N-ch MOS transistor 51-n are arranged in the height direction. These pairs of the P-ch MOS transistor 50-n and the N-ch MOS transistor 51-n are arranged in the width direction in FIG. 18 at a spacing approximately equal to that of the memory cells MC in the width direction.
Also, in the sense amplifier block 1015, pairs of one P-ch MOS transistor 52-m and one N-ch MOS transistor 53-m are arranged in the height direction. Here, the number of pairs of the P-ch MOS transistor 52-m and the N-ch MOS transistor 53-m included in the sense amplifier block 1015 is half of the number of pairs of the P-ch MOS transistor 50-n and the N-ch MOS transistor 51-n included in the switch block 1012. One pair of the P-ch MOS transistor 52-m and the N-ch MOS transistor 53-m in the sense amplifier block 1015 is provided to every other pair of the P-ch MOS transistor 50-n and the N-ch MOS transistor 51-n in the switch block 1012. Specifically, as shown in FIG. 18, a pair of the P-ch MOS transistor 52-m and the N-ch MOS transistor 53-m is placed at the lower side of a pair of the P-ch MOS transistor 50-n and the N-ch MOS transistor 51-n where n is an even number.
As described above, in the conventional memory, the spacing of the transistors in the word driver block 1006, the row decoder block 1007, the switch block 1012, and the sense amplifier block 1015 depends on the spacing of the memory cells in the memory cell array 1001. Also, with the above configuration being applied to the respective components of the memory, data can be written into or read from the memory cells. Such a conventional memory is exemplarily disclosed in Japanese Patent Laid-Open Publication No. 2001-344989 (p. 9, FIG. 1).
Here, of diffusion layers (sources and drains) of the N-ch MOS transistors 30-k, 51-n, and 53-m and the P-ch MOS transistors 31-k, 50-n, and 52-m shown in FIGS. 16 and 18, adjacent diffusion layers are isolated through Shallow Trench Isolation (STI). As such, when the adjacent diffusion layers are isolated through STI, a large stress occurs between an oxide film for isolation and the diffusion layers, thereby causing a large number of defects in the vicinity of an interface between the oxide film and the diffusion layers. With such defects in the vicinity of a gate electrode, an electric current flowing through the N-ch MOS transistor is reduced. However, such occurrence of defects has not posed a significant problem in the conventional technology because a distance La from a gate electrode to an end of a diffusion layer shown in FIGS. 16 and 18 is relatively long.
However, in recent years, microfabrication of elements, such as transistors, has been in rapid progress. Also, in designing of memories or the like, a minimum value or a value close to the minimum value in design rules is used in general. Therefore, compared with the conventional technology, the distance La from the gate electrode to the end of the diffusion layer in the N-ch MOS transistors 30-k, 51-n, and 53m exemplarily shown in FIGS. 16 and 18 has become shortened. As such, with the distance La from the gate electrode to the end of the diffusion layer being shortened, a reduction of the electric current in the N-ch MOS transistors 30-k, 51-n, and 53-m becomes significant, thereby destablizing the operation of the memory.
The above-described problem can be solved exemplarily by increasing the distance from the gate electrode to the end of the diffusion layer of the N-ch MOS transistor. This makes it possible to prevent the amount of electric current flowing through the N-ch MOS transistor from being reduced due to defects caused by stress in the vicinity of the interface between the oxide film and the diffusion layers.
However, as the distance between the gate electrode to the end of the diffusion layer is increased, the spacing of the transistors is also increased. This hinders a semiconductor memory device from being made compact.
Moreover, as described above, the spacing of the transistors in the word driver block 1006, the sense amplifier block 1015, and the switch block 1012 depends on the spacing of the memory cells in the memory cell array. For example, the N-ch MOS transistors 30-k in the word driver block 1006 are arranged at a spacing approximately equal to that of the memory cells MC in the memory cell array. Therefore, as the distance from the gate electrode to the end of the diffusion layer of the N-ch MOS transistor 30-k is increased, the spacing of the N-ch MOS transistors are not matched with the spacing of the memory cells MC.